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? semiconductor components industries, llc, 2012 may, 2012 ? rev. 3 1 publication order number: ncp1392/d ncp1392b, ncp1392d high-voltage half-bridge driver with inbuilt oscillator the ncp1392b/d is a self ? oscillating high voltage mosfet driver primarily tailored for the applications using half bridge topology. due to its proprietary high ? voltage technology, the driver accepts bulk voltages up to 600 v. operating frequency of the driver can be adjusted from 25 khz to 480 khz using a single resistor. adjustable brown ? out protection assures correct bulk voltage operating range. an internal 100 ms or 12.6 ms pfc delay timer guarantee that the main downstream converter will be turned on in the time the bulk voltage is fully stabilized. the device provides fixed dead time which helps lowering the shoot ? through current. features ? wide operating frequency range ? from 25 khz to 480 khz ? minimum frequency adjust accuracy 3% ? fixed dead time ? 0.6 s or 0.3 s ? adjustable brown ? out protection for a simple pfc association ? 100 ms or 12.6 ms pfc delay timer ? non ? latched enable input ? internal 16 v v cc clamp ? low startup current of 50 a ? 1 a / 0.5 a peak current sink / source drive capability ? operation up to 600 v bulk voltage ? internal temperature shutdown ? soic ? 8 package ? these are pb ? free devices typical applications ? flat panel display power converters ? low cost resonant smps ? high power ac/dc adapters for notebooks ? offline battery chargers ? lamp ballasts device package shipping ? ordering information NCP1392BDR2G soic ? 8 (pb ? free) 2500 / tape & reel marking diagrams http://onsemi.com 1 8 soic ? 8 case 751 1392x alyww 1 8 1392x = specific device code x = b or d a = assembly location l = wafer lot y = year ww = work week = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. pinout diagram vcc rt bo gnd vboot mupper hb mlower ncp1392ddr2g soic ? 8 (pb ? free) 2500 / tape & reel
ncp1392b, ncp1392d http://onsemi.com 2 figure 1. typical application example + + pfc front stage rbo2 rf rfmax rfstart cbulk rbo1 dboot vcc rt bo gnd vboot mupper hb mlower cboot m2 ncp1392 dc output ac output css m1 pin function description pin # pin name function pin description 1 v cc supplies the driver the driver accepts up to 16 v (given by internal zener clamp) 2 rt timing resistor connecting a resistor between this pin and gnd, sets the operating frequency 3 bo brown ? out detects low input voltage conditions. when brought above vref_en, it stops the driver. operation is restored (without any delay) when bo pin voltage drops 100 mv below vref_en. 4 gnd ic ground 5 mlower low ? side driver output drives the lower side mosfet 6 hb half ? bridge connection connects to the half ? bridge output 7 mupper high ? side driver output drives the higher side mosfet 8 vboot bootstrap pin the floating supply terminal for the upper stage
ncp1392b, ncp1392d http://onsemi.com 3 ? + ? + ? + ? + 20 s filter high level for 50ms after v cc on vref bo ? + vref en sw i hyster bo v cc rt v cc management pon reset tsd v cc clamp v cc v dd v ref pfc delay (100ms) v ref v dd ? + v ref i dt c t s d r clk q q pulse trigger level shifter uv detect delay s r q q v boot m upper bridge m lower gnd v cc figure 2. internal circuit architecture (b version) 0.5 s filter
ncp1392b, ncp1392d http://onsemi.com 4 ? + ? + ? + 20 s filter high level for 6.3 ms after v cc on vref bo sw i hyster bo v cc rt v cc management pon reset tsd v cc clamp v cc v dd v ref pfc delay (12.6 ms) v ref v dd ? + v ref i dt c t s d r clk q q pulse trigger level shifter uv detect delay s r q q v boot m upper bridge m lower gnd v cc figure 3. internal circuit architecture (d version)
ncp1392b, ncp1392d http://onsemi.com 5 maximum ratings table symbol rating value unit vbridge high voltage bridge pin ? pin 6 ? 1 to +600 v vboot ? vbridge floating supply voltage 0 to 20 v vdrv_hi high ? side output voltage vbridge ? 0.3 to vboot + 0.3 v vdrv_lo low ? side output voltage ? 0.3 to v cc +0.3 v dvbridge/dt allowable output slew rate 50 v/ns i cc maximum current that can flow into v cc pin (pin 1), (note 1) 20 ma v_rt rt pin voltage ? 0.3 to 5 v maximum voltage, all pins (except pins 4 and 5) ? 0.3 to 10 v r ja thermal resistance junction ? to ? air, ic soldered on 50 mm 2 cooper 35 m 178 c/w r ja thermal resistance junction ? to ? air, ic soldered on 200 mm 2 cooper 35 m 147 c/w storage temperature range ? 60 to +150 c esd capability, human body model (all pins except hv pins 6, 7 and 8) 2.0 kv esd capability, human body model (hv pins 6, 7 and 8) 1.5 kv esd capability, machine model 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device contains internal zener clamp connected between v cc and gnd terminals. current flowing into the v cc pin has to be limited by an external resistor when device is supplied from supply which voltage is higher than vcc clamp (16 v typically). the i cc parameter is specified for vbo = 0 v.
ncp1392b, ncp1392d http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v, unless otherwise noted) characteristic pin symbol min typ max unit supply section turn ? on threshold level, v cc going up 1 vcc on 10 11 12 v minimum operating voltage after turn ? on 1 vcc min 8 9 10 v startup voltage on the floating section 1 vboot on 7.8 8.8 9.8 v cutoff voltage on the floating section, 1 vboot min 7 8 9 v v cc level at which the internal logic gets reset 1 vcc reset ? 6.5 ? v startup current, v cc < vcc on , 0 c t amb +125 c 1 i cc ? ? 50 a startup current, v cc < vcc on , ? 40 c t amb < 0 c 1 i cc ? ? 65 a internal ic consumption, no output load on pins 8/7 ? 5/4, fsw = 100 khz 1 i cc 1 ? 2.2 ? ma internal ic consumption, 1 nf output load on pins 8/7 ? 5/4, fsw = 100 khz 1 i cc 2 ? 3.4 ? ma consumption in fault mode (drivers disabled, v cc > v cc(min) , r t = 3.5 k ) 1 i cc 3 ? 2.56 ? ma consumption during pfc delay period, 0 c t amb +125 c i cc 4 ? ? 400 a consumption during pfc delay period, ? 40 c t amb < 0 c i cc 4 ? ? 470 a internal ic consumption, no output load on pin 8/7 f sw = 100 khz 8 i boot1 ? 0.3 ? ma internal ic consumption, 1 nf load on pin 8/7 f sw = 100 khz 8 i boot2 ? 1.44 ? ma consumption in fault mode (drivers disabled, v boot > vboot min ) 8 i boot3 ? 0.1 ? ma v cc zener clamp voltage @ 20 ma 1 vcc clamp 15.4 16 17.5 v internal oscillator minimum switching frequency (r t = 35 k on pin 2 for d t = 600 ns, r t = 70 k on pin 2 for d t = 300 ns) 2 f sw min 24.25 25 25.75 khz maximum switching frequency (b version), r t = 3.5 k on pin 2, d t = 600 ns 2 f sw maxb 208 245 282 khz maximum switching frequency (d version), r t = 3.5 k on pin 2, d t = 300 ns 2 f sw maxd 408 480 552 khz reference voltage for all current generations 2 v ref rt 3.33 3.5 3.67 v internal resistance discharging c soft ? start 2 rt discharge ? 500 ? operating duty cycle symmetry 5, 7 dc 48 50 52 % note: maximum capacitance directly connected to pin 2 must be under 100 pf. drive output output voltage rise time @ cl = 1 nf, 10 ? 90% of output signal 5, 7 t r ? 40 ? ns output voltage fall time @ cl = 1 nf, 10 ? 90% of output signal 5, 7 t f ? 20 ? ns source resistance 5, 7 r oh ? 12 ? sink resistance 5, 7 r ol ? 5 ? deadtime (b version) 5,7 t deadb 540 610 720 ns deadtime (d version) 5,7 t deadd 260 305 360 ns leakage current on high voltage pins to gnd (600 vdc) 6,7,8 ihv leak ? ? 5 a protection brown ? out input bias current 3 ibo bias ? 0.01 ? a brown ? out level 3 vbo 0.95 1 1.05 v hysteresis current, v pin3 < vbo 3 ibo 15.6 18.2 20.7 a reference voltage for en input (b version) 3 v ref en 1.9 2 2.1 v en comparator (not available in d version) ? v ref en_d ? ? ? v enable comparator hysteresis 3 en_hyste ? 100 ? mv propagation delay before drivers are stopped 3 en_delay ? 0.5 ? s delay before any driver restart (b version) ? pfc delay ? 100 ? ms delay before any driver restart (d version) ? pfc delay ? 12.6 ? ms temperature shutdown ? tsd 140 ? ? c hysteresis ? tsdhyste ? 30 ? c
ncp1392b, ncp1392d http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v, unless otherwise noted) characteristic unit max typ min symbol pin protection brown out discharge time (b version) (note 2) ? bodisch ? 50 ? ms brown out discharge time (d version) (note 2) ? bodisch ? 6.3 ? ms 2. guaranteed by design.
ncp1392b, ncp1392d http://onsemi.com 8 typical characteristics 11.01 11.00 10.99 10.98 10.97 10.96 10.95 10.94 10.93 10.92 10.91 ? 40 ? 20 0 20 40 60 80 100 120 voltage (v) temperature ( c) ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) voltage (v) 8.98 8.97 8.96 8.95 8.94 8.93 8.92 8.91 8.90 figure 4. v ccon figure 5. v ccmin voltage (v) ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) figure 6. v booton 8.85 8.80 8.75 8.70 8.65 8.60 8.55 temperature ( c) figure 7. v bootmin ? 40 ? 20 0 20 40 60 80 100 120 voltage (v) 8.10 8.05 8.00 7.95 7.90 7.85 7.80 7.75 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) figure 8. r oh 20 18 16 14 12 10 8 6 4 2 0 temperature ( c) figure 9. r ol ? 40 ? 20 0 20 40 60 80 100 120 8 7 6 5 4 3 2 1 0 resistance ( ) resistance ( )
ncp1392b, ncp1392d http://onsemi.com 9 typical characteristics ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) figure 10. f swmax (b version) frequency (khz) 243.4 temperature ( c) figure 11. f swmax (d version) ? 40 ? 20 0 20 40 60 80 100 120 frequency (khz) 25.05 25.00 24.95 24.90 24.85 24.80 24.75 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) figure 12. f swmin (b version) 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 450 temperature ( c) figure 13. f swmin (d version) ? 40 ? 20 0 20 40 60 80 100 120 400 350 300 250 200 150 100 50 0 figure 14. i cc_startup figure 15. i cc4 current ( a) current ( a) 243.2 243.0 242.8 242.6 242.4 242.2 242.0 241.8 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) frequency (khz) 490 485 480 475 470 465 460 455 450 temperature ( c) ? 40 ? 20 0 20 40 60 80 100 120 frequency (khz) 24.92 24.90 24.88 24.86 24.84 24.82 24.80 25.00 24.98 24.96 24.94
ncp1392b, ncp1392d http://onsemi.com 10 typical characteristics figure 16. t dead (b version) temperature ( c) figure 17. t dead (d version) ? 40 ? 20 0 20 40 60 80 100 120 2.008 voltage (v) 2.006 2.004 2.002 2.000 1.998 1.996 1.994 1.992 1.990 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) figure 18. pfc delay (b version) voltage (v) 1.015 1.014 1.013 1.012 1.011 1.010 1.009 1.008 1.007 figure 19. pfc delay (d version) figure 20. v ref_en figure 21. v bo time (ns) 645 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) 640 635 630 625 620 615 610 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) time (ns) 330 325 320 315 310 305 300 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) time (ms) 14.0 13.5 13.0 12.5 12.0 11.5 11.0 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) 109 time (ms) 108 107 106 105 104 103 102 101 100 90
ncp1392b, ncp1392d http://onsemi.com 11 typical characteristics i rt (ma) figure 22. r t _ discharge 0.2 frequency (khz) 290 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 240 190 140 90 40 figure 23. en hyste figure 24. i bo figure 25. v cc_clamp figure 26. i rt and appropriate frequency (b version) temperature ( c) ? 40 ? 20 0 20 40 60 80 100 120 voltage (v) 17.0 16.8 16.6 16.4 16.2 16.0 15.8 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) 19.4 19.2 19.0 18.8 18.6 18.4 18.2 18.0 17.8 17.6 17.4 current ( a) voltage (mv) 110 108 106 104 102 100 98 96 94 92 90 ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) figure 27. i rt and appropriate frequency (d version) ? 40 ? 20 0 20 40 60 80 100 120 temperature ( c) 580 560 540 520 500 480 460 440 420 400 resistance ( ) i rt (ma) 0.2 frequency (khz) 600 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 400 300 200 100 0 500 0.0 0.1
ncp1392b, ncp1392d http://onsemi.com 12 application information the ncp1392 is primarily intended to drive low cost half bridge applications and especially resonant half bridge applications. the ic includes several features that help the designer to cope with resonant spms design. all features are described thereafter: ? wide operating frequency range : the internal current controlled oscillator is capable to operate over wide frequency range. minimum frequency accuracy is 3%. ? fixed dead ? time : the internal dead ? time helping to fight with cross conduction between the upper and lower power transistors. three versions with different dead time values are available to cover wide range of applications. ? pfc timer : fixed delay is placed to ic operation whenever the driver restarts (vcc on or bo_ok detect events). this delay assures that the bulk voltage will be stabilized in the time the driver provides pulses on the outputs. another benefit of this delay is that the soft start capacitor will be full discharged before any restart. ? brown ? out detection : the bo input monitors bulk voltage level via resistor divider and thus assures that the application is working only for wanted bulk voltage band. the bo input sinks current of 18.2 a until the vref bo threshold is reached. designer can thus adjust the bulk voltage hysteresis according to the application needs. ? non ? latched enable input : the enable comparator input is connected in parallel to the bo terminal to allow the designer stop the output drivers when needed. there is no pfc delay when enable input is released so skip mode for resonant smps applications and dimming for light ballast applications are possible. ? internal v cc clamp : the internal zener clamp offers a way to prepare passive voltage regulator to maintain v cc voltage at 16 v in case the controller is supplied from unregulated power supply or from bulk capacitor. ? low startup current : this device features maximum startup current of 50 a which allows the designer to use high value startup resistor for applications when driver is supplied from the auxiliary winding. power dissipation of startup resistor is thus significantly reduced. current controlled oscillator the current controlled oscillator features a high ? speed circuitry allowing operation from 50 khz up to 960 khz. however, as a division by two internally creates the two q and q outputs, the final effective signal on output mlower and mupper switches in half frequency range. the vco is configured in such a way that if the current that flows out from the rt pin increases, the switching frequency also goes up. figure 28 shows the architecture of this oscillator. figure 28. the internal current controlled oscillator architecture ? + ? + delay v ref rt from pfc delay c t r t r t v ref s d clk r i dt q q from en cmp. pon reset v dd a b dead time c soft ? start + ? + ? r soft ? start the internal timing capacitor ct is charged by current which is proportional to the current flowing out from the rt pin. the discharging current i dt is applied when voltage on this capacitor reaches 2.5 v. the output drivers are disabled during discharge period so the dead time length is given by the discharge current sink capability. discharge sink is disabled when voltage on the timing capacitor reaches zero and charging cycle starts again. the charging current and thus also whole oscillator is disabled during the pfc delay period to keep the ic consumption below 400 a.
ncp1392b, ncp1392d http://onsemi.com 13 this is valuable for applications that are supplied from auxiliary winding and v cc capacitor is supposed to provide energy during pfc delay period. for the resonant applications and light ballast applications it is necessary to adjust minimum operating frequency with high accuracy. the designer also needs to limit maximum operating and startup frequency. all these parameters can be adjusted using few external components connected to the rt pin as depicted in figure 29. figure 29. typical rt pin connection r fmax r t v cc r t r fstart r bias r fmax ? ocp r comp c comp c ss d1 tlv431 (to primary current sensor) (to secondary voltage regulator) ncp1392 voltage feedback current feedback the minimum switching frequency is given by the rt resistor value. this frequency is reached if there is no optocoupler or current feedback action and soft start period has been already finished. the maximum switching frequency excursion is limited by the rf max selection. note that the f max value is influenced by the optocoupler saturation voltage value. resistor rfstart together with capacitor c ss prepares the soft start period after pfc timer elapses. the rt pin is grounded via an internal switch during the pfc delay period to assure that the soft start capacitor will be fully discharged via rfstart resistor. there is a possibility to connect other control loops (like current control loop) to the rt pin. the only one limitation lies in the rt pin reference voltage which is vref rt = 3.5 v. used regulator has to be capable to work with voltage lower than vref rt . the tlv431 shunt regulator is used in the example from figure 4 to prepare current feedback loop. diode d1 is used to enable regulator biasing via resistor rbias. total saturation voltage of this solution is 1.25 + 0.6 = 1.85 v for room temperature. shottky diode will further decrease saturation voltage. rf max ? ocp resistor value, limits the maximum frequency that can be pushed by this regulation loop. this parameter is not temperature stable because of the d1 temperature drift. brown ? out protection the brown ? out circuitry (bo) offers a way to protect the application from low dc input voltages. below a given level, the controller blocks the output pulses, above it, it authorizes them. the internal circuitry, depicted by figure 30, offers a way to observe the high ? voltage (hv) rail.
ncp1392b, ncp1392d http://onsemi.com 14 figure 30. the internal brown ? out configuration with an offset current sink ? + r upper bo r lower v refbo i bo sw 20 s filter v bulk high level for bodisch time after v cc on bo_ok to and gates to pfc delay + ? a resistive divider made of r upper and r lower , brings a portion of the hv rail on pin 3. below the turn ? on level, the 18.2 a current sink (ibo) is on. therefore, the turn ? on level is higher than the level given by the division ratio brought by the resistive divider. to the contrary, when the internal bo_ok signal is high (pfc timer runs or mlower and mupper pulse), the i bo sink is deactivated. as a result, it becomes possible to select the turn ? on and turn ? off levels via a few lines of algebra: ibo is on vref bo v bulk1 r lower r lower r upper i bo r lower r upper r lower r upper (eq. 1) ibo is off vref bo v bulk2 r lower r lower r upper (eq. 2) we can extract r lower from equation 2 and plug it into equation 1, then solve for r upper : r lower vref bo v bulk1 v bulk2 i bo v bulk2 vref bo (eq. 3) r upper r lower v bulk2 vref bo vref bo (eq. 4) if we decide to turn ? on our converter for v bulk1 equals 350 v and turn it off for v bulk2 equals 250 v, then for i bo = 18.2 a and vref bo = 1.0 v we obtain: r upper = 5.494 m r lower = 22.066 k the bridge power dissipation is 400 2 / 5.517 m = 29 mw when front ? end pfc stage delivers 400 v. figure 31 simulation result confirms our calculations.
ncp1392b, ncp1392d http://onsemi.com 15 figure 31. simulation results for 350/250 on/off brown ? out levels the ibo current sink is turned on for bodisch time after any controller restart to let the bo input voltage stabilize (there can be connected big capacitor to the bo input and the ibo is only 18.2 a so it will take some time to dischar ge). once the bodisch time one shoot pulse ends the bo comparator is supposed to either hold the i bo sink turned on (if the bulk voltage level is not sufficient) or let it turned off (if the bulk voltage is higher than v bulk1 ). see figures 10 ? 13 for better understanding on how the bo input works. figure 32. bo input functionality ? v bulk2 < v bulk < v bulk1 vbulk vbo bo_ok vcc drv_en vbulk_on vbulk_off 1 v ibo is turned on after vcc_on by internal logic (for bodisch time) < bodisch
ncp1392b, ncp1392d http://onsemi.com 16 figure 33. bo input functionality ? v bulk2 < v bulk < v bulk1 , pfc start follows vbulk vbo bo_ok vcc drv_en vbulk_on vbulk_off 1 v pfcdelay figure 34. bo input functionality ? v bulk > v bulk1 vbulk vbo bo_ok vcc drv_en vbulk_on vbulk_off 1 v checking vbo by activating ibo sink, released after bodisch time bodisch the drivers are activated with delay specify by pfcdelay after vcc_on, ibo sing has been turned off by bodisch time after vcc_on, bo capacitor had enough time to charge pfcdelay
ncp1392b, ncp1392d http://onsemi.com 17 figure 35. bo input functionality ? v bulk < v bulk2 , pfc start follows vbulk vbo bo_ok vcc drv_en vbulk_on vbulk_off 1 v pfcdelay non ? latched enable input (b version only) the non ? latched input stops output drivers immediately the bo terminal voltage grows above 2 v threshold. the enable comparator features 100 mv hysteresis so the bo terminal has to go down below 1.9 v to recover ic operation. this input offers other features to the ncp1392 like dimming function for lamp ballasts (figure 36) or skip mode capability for resonant converters (figures 37 and 39). figure 36. dimming feature implementation using nonlatched input on bo terminal ? + ? + q2 r2 r3 r4 r1 d1 q1 gnd to and gates to and gates sw v refbo v refen r upper bo r lower 20 s filter v bulk r t r fstart c ss rt v cc dimming input ncp1392 i hyste high level for bodisch time after v cc on to pfc delay 0.5 s filter + ? + ?
ncp1392b, ncp1392d http://onsemi.com 18 the dimming feature can be easily aid to the ballast application by adding two bipolar transistors (figure 14). transistor q2 pullup bo input when dimming signal is high. in the same time the q1 discharges soft start capacitor via diode d1. ballast application is enabled (including soft ? start phase) when dimming signal becomes low again. figure 37. skip mode feature implementation (temperature dependent, cost effective) ? + ? + r1 voltage r2 gnd to and gates to and gates sw v refbo v refen r upper bo r lower 20 s filter v bulk r t r fstart c ss rt ncp1392 feedback d1 i hyste high level for bodisch time after v cc on to pfc delay 0.5 s filter + ? + ? figure 38. skip mode with transistor feature implementation (temperature dependent, cost effective) ? + ? + r4 voltage r5 gnd to and gates to and gates sw v refbo v refen r upper bo r lower 20 s filter v bulk r t r fstart c ss rt ncp1392 feedback i hyste c1 r6 r3 r2 r1 v cc q1 high level for bodisch time after v cc on to pfc delay q2 soft ? start after skip (if needed) d1 + ? ? + ? 0.5 s filter
ncp1392b, ncp1392d http://onsemi.com 19 figure 39. skip mode feature implementation (better accuracy) ? + ? + r4 voltage r5 gnd to and gates to and gates sw v refbo v refen r upper bo r lower 20 s filter v bulk r t r fstart c ss rt ncp1392 feedback i hyste ic1 tlv431 c1 r6 r3 r2 r1 v cc q1 high level for bodisch time after v cc on to pfc delay 0.5 s filter + ? + ? figures 37 and 39 shows skip mode feature implementation using ncp1392 driver. voltage across resistor r1 (r4) increases when converter enters light load conditions. the enable comparator is triggered when voltage across r1 is higher than vref en + vf(d1) for connection from figure 37 (voltage across r4 is higher than 1.24 v for connection from figure 16). ic then prevents outputs from pulsing until bo terminal voltage decreases below 1.92 v. note that enable comparator serves also as an automatic overvoltage protection. when bulk voltage is too high, the enable input is triggered via bo divider. following equations can be used for easy calculations of devices connected to rt pin: minimum frequency: r t 3.5 k frequency q (eq. 5) maximum frequency where soft ? start begins: r fstart 3.5 k r t frequency r t r t q 3.5 k (eq. 6) the soft ? start duration is set by css capacitor: c ss ss duration r fstart 5 (eq. 7) a resistor to set maximum frequency, if the optocoupler is fully conductive is calculated by the following equation: r (r4 r5) ? ? 3.5 v ce_sat k r t frequency r t ? r t q ? 3.5 k k v ce_sat (eq. 8) the constants in the equations are as follows: version b: k = 244.4 10 6 , q = 0.555 10 3 version d: k = 478.9 10 6 , q = 1.053 10 3
ncp1392b, ncp1392d http://onsemi.com 20 the high ? voltage driver figure 40 shows the internal architecture of the high ? voltage section. the device incorporates an upper uvlo circuitry that makes sure enough v gs is available for the upper side mosfet. the v cc for floating driver section is provided by c boot capacitor that is refilled by external bootstrap diode. figure 40. the internal high ? voltage section of the ncp1392 hgd delay uv detect hb v cc lgd gnd pulse trigger level shifter from latch high if ok from pfc delay boot s r q q c boot a b dead time a b + d boot v aux v bulk the a and b outputs are delivered by the internal logic, as depicted in block diagram. this logic is constructed in such a way that the mlower driver starts to pulse firs after any driver restart. the bootstrap capacitor is thus charged during first pulse. a delay is inserted in the lower rail to ensure good matching between these propagating signals. as stated in the maximum rating section, the floating portion can go up to 600 vdc and makes the ic perfectly suitable for offline applications featuring a 400 v pfc front ? end stage.
ncp1392b, ncp1392d http://onsemi.com 21 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp1392/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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